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VHDL

VHDL stands for “very high-speed integrated circuit hardware description language.” It is a programming language that is used to model a digital system by means of data flow, behavioural and structural modelling. This language was first introduced in 1981 by the American Department of Defence as part of the VHSIC program.

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What does a VHDL developer do?

VHDL is generally used to write text models that describe a logistic circuit. Such a model is then processed by a synthesis program. A simulation program is used to test the logistic design with the help of simulation models. This way, the logistic circuits that make up the interface of the design are portrayed. This collection of simulation models is usually called a testbench. A VHDL simulator is typically an event-driven simulator. This means that every operation is added to an event waiting list for a specifically planned time.

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Superhero Tom
VHDL developer

In daily life, he plays field hockey and is studying for his master’s degree in Electrical Engineering at TU Delft.

Een foto van een voorbeeldstudent.
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